Semiconductor devices are typically manufactured in a bulk silicon substrate. However, when the silicon substrate is used, it is difficult to form a source region and a drain region with a small thickness. In addition, parasitic junction capacitance formed at an interface between the silicon substrate and the source and drain regions typically increases with smaller dimensions and may reduce operating speed.
In order to solve these problems, a semiconductor device having a silicon-on-insulator (SOI) structure has been developed. In the semiconductor device having a SOI structure, an insulator electrically insulates a bottom silicon substrate from a silicon layer formed above the bottom silicon substrate. A unit device is formed on the silicon layer. As will be understood by those skilled in the art, the electrical isolation results in a decrease in junction electrostatic capacitance generated between unit devices formed within an IC chip. In addition, a semiconductor device having an SOI structure may exhibit a decreased short channel effect, an increased sub-threshold swing, high mobility, and a decreased hot carrier effect compared to other conventional semiconductor devices.
However, a semiconductor device having an SOI structure includes an active region isolated from the silicon substrate, contrary to other conventional semiconductor devices. Therefore, a body contact is typically not formed, which means that SOI structures are prone to a floating body effect. The floating body effect occurs when excess carriers collect in a floating body during the operation of the semiconductor device, resulting in parasitic bipolar-driven breakdown and latch-up.
A semiconductor device having a quasi-SOI structure has been developed to solve this problem. A semiconductor device having a quasi-SOI structure has a body contact. That is, a contact hole is formed under a portion of the active region to allow excess carriers to be removed.
FIG. 1 is a cross sectional view of a semiconductor device having a conventional quasi-SOI structure. Referring to FIG. 1, an insulator 10 is formed only under a source region 3 and a drain region 5. As a result, the source region 3 and the drain region 5 are insulated from a bottom silicon substrate 1 by the insulator 10. Therefore, the semiconductor device having the conventional quasi-SOI structure has body contact in the same way as other conventional semiconductor devices. The semiconductor device of FIG. 1 further includes an isolation layer 2, a gate oxide layer 7, and a gate electrode 9.
The semiconductor device having the quasi-SOI structure may be manufactured using a following method. In a first method, oxygen ions are implanted into a bottom silicon substrate 1 using a gate electrode 9 as a mask, and the bottom silicon substrate 1 is oxidized by a high temperature thermal treatment to form an insulator 10. Therefore, in this case, the insulator 10 is formed after the gate electrode 9 is formed. However, the ion implantation and the heat treatment may adversely affect the gate oxide layer 7 and a channel ion implantation state. In a second method, an insulating material such as an oxide layer is deposited on a bottom silicon substrate 1, and patterned to form a patterned insulator 10. Then, silicon is deposited on the patterned insulator 10 by epitaxial growth, and a gate electrode 9 is patterned over the epitaxial silicon. However, when the gate electrode 9 is patterned using photolithography, the gate electrode 9 can be misaligned with the insulator 10, and this misalignment may result in device failure.